This application relates to integrated circuit design automation and, specifically, to interconnect coupling noise estimation.
From the point of view of integrated circuit (IC) analysis, transfer characteristics are a common thread that runs through essentially all integrated circuit elements. Transfer characteristics represent the behavior of IC elements, including their speed of switching from one state to the other in response to a voltage inducement.
A typical IC includes an array of IC elements that forms one or more multistage circuits. IC elements are selected from a library of cells also known as gates. In the IC, the gates are interconnected by a pattern of conductive material lines that carry signals (voltage, current) between the gates. Interconnect lines are frequently referred to as interconnect wires or, simply, interconnects.
In deep submicron ICs, adjacent interconnect lines are placed in close proximity to each other. The close proximity between interconnect lines forms therebetween a parasitic element in the form of capacitive coupling. Crosstalk between the interconnect lines results from this capacitive coupling (inductive coupling is not addressed.) For example, when a signal is carried by an interconnect line between cascaded gates of a multistage circuit this signal influences additional gate(s) connected to a different, closely proximate interconnect line. The coupling capacitance grows with increases in the average length and routing density of interconnect lines. Hence crosstalk becomes more critical at faster gate switching speeds.
In general, noise voltage can be generated internally in a gate or introduced into the gate. Internally in the gate, noise voltage represents inherent random energy produced by thermal agitation or fluctuation in the number of charge carriers that flow within the gate. Crosstalk introduces noise voltage into the gate due to the capacitive coupling between adjacent interconnect lines. Crosstalk noise voltage is also referred to as interconnect coupling noise.
If a noise voltage is induced into a gate, the noise voltage can cause a spurious transition from one state to another. Because interconnect coupling noise can cause gates to falsely switch from one state to the other, interconnect coupling noise increasingly limits the performance of high-speed VLSI (very large scale integration) circuits.
Circuit modeling is a useful method for estimating interconnect coupling noise values. Circuit modeling is an approximation of gates and interconnect lines. Networklike circuit-models include circuit elements such as resistances and capacitances for approximating the gates and interconnect lines.
Several methods exist for estimating interconnect coupling noise. One of the methods, a noise prediction method using a capacitance value multiplied by a switching factor, is not accurate nearly enough because this method produces highly optimistic or pessimistic predictions. This method uses the capacitance value to model the coupling capacitance between a pair of adjacent interconnect lines. The switching factor is slightly more than zero for a pair of lines switching in the same direction, and slightly less than two for a pair of lines switching in the opposite direction.
Alternatively, some conventional methods use an L model for modeling interconnect lines. However, such methods include specific assumptions and provide noise estimation and analysis only for a step input voltage. One of the assumptions for cascaded gates (i.e., a driver gate in series with and driving a load gate) is:
Rdriver less than  less than Rinterconnect;
and
Cload less than  less than Cinterconnect,
where, Rdriver approximates the driver, Cload approximates the input impedance of the load gate, and Rinterconnect and Cinterconnect represent the interconnect line.
Furthermore, such methods iteratively evaluate the noise for different resistance-capacitance ratios. The specific assumptions are made in each iteration. As a special case, some of these methods do not take into account the interconnect resistance while deriving noise expressions. That is, the interconnect resistance is assumed to be zero ohms. Also, the error in noise estimation based on electrical properties of modeled circuits increases as the rise time decreases.
Design automation tools use circuit modeling in pre-layout estimation of IC behavior and in post-layout IC performance analysis. Accurate estimation and analysis depend closely on accurate modeling. Thus, efficient and more accurate modeling is needed. The present invention addresses these and related issued.
The present invention provides a more accurate interconnect coupling noise estimation. A preferred embodiment of the present invention provides noise estimation for coupled interconnects in deep submicron integrated circuits. By providing more accurate circuit modeling techniques that employ L and Π models, the invention produces a more accurate yet more general noise estimation. The accuracy achieved in the Π model case is superior.
The L and Π models are driven by one of or, one at a time, a plurality of input voltages having step, ramp or other waveforms Namely, the principles of the invention apply equally well to input voltages with other than step or ramp wave-forms because input voltages of other wave-forms can be expressed, for example, as a piece-wise series of ramps. In other words, the invention provides a more accurate interconnect coupling noise estimation for any input voltage, whether having step, ramp or other wave-form.
With these circuit modeling techniques, analytical expressions of a noise voltage at a victim interconnect line describe the impact of capacitive coupling between an aggressor interconnect line and the victim interconnect line. Any one of a plurality of aggressor interconnect lines that is proximate to the victim interconnect line may be capacitively coupled to the victim interconnect line. Hence, signal activity at any of such aggressor interconnect lines produces an impact on the victim interconnect line via the respective capacitive coupling. As indicated, this impact can be determined for input voltages having step, ramp or any other wave-forms.
In accordance with a purpose of the invention, a computer system can be used in which an embodiment of the invention is implemented. The invention can be implemented in the computer system as a separate tool or as part of other design automation tools. For implementing an embodiment of the invention in the computer system, the principles presented above can be stored in a computer readable medium in the form of computer program code. Moreover, the library of cells (gate library) may be stored in a computer readable medium. The computer readable medium includes internal or external, fixed or removable, computer memory.
The improved modeling accuracy and, in turn, the more accurate interconnect coupling noise predictions are advantageous in several respects. One advantage is improved analysis of circuit performance sensitivity to various interconnect tuning parameters. Another advantage is the lesser overdesign and guardbanding in high-performance designs. Yet another advantage is the shorter runtime it takes to analyze the circuits when using a computer to embody the invention. These advantages apply at all stages of a performance-convergent synthesis and layout methodology. Finally, the approach presented herein can be advantageously used as an analytical tool to estimate the impact of noise voltage peaks early on in the physical design cycle of integrated circuits such as microprocessors, ASIC (application specific IC) or any other custom-designed IC.
In accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to noise estimation for coupled interconnects in deep submicron integrated circuits. One aspect of the invention is a method for interconnect coupling noise estimation. Another aspect of the invention is a computer readable medium embodying computer program code. The computer program code is configured to cause a computer to perform steps for estimating the interconnect coupling noise.
The interconnect coupling noise estimation includes modeling a circuit, where capacitive (and not inductive) coupling is included. The circuit includes a pair of interconnects each connecting between a driver gate and a load gate, where signal activity at a first interconnect of the pair of interconnects is having an impact on a second interconnect of the pair of interconnects. The circuit modeling includes modeling the first and second interconnects, the driver gate and the load gate.
A driver gate is modeled using a Thxc3xa9venin equivalent where the gate is replaced by an input voltage source in series with a resistance. A load gate is modeled by a capacitance that approximates the input impedance of the load gate.
The noise estimation further includes expressing transfer characteristics of the modeled circuit for one of or, each one at a time, for the plurality of input voltages including the step and ramp input voltages. Additionally, the noise estimation includes expressing a voltage at the second interconnect based on the transfer characteristics. The voltage, in turn, represents the interconnect coupling noise at the victim interconnect line due to the capacitive coupling between the aggressor and interconnect lines. Namely, accounting for the capacitive coupling between the first (aggressor) and second (victim) interconnect lines, the transfer characteristics determine the voltage at the interconnect line. In fact, the transfer characteristics may be also referred to as coupling transfer characteristics.
The noise estimation further includes determining a peak value of the interconnect coupling noise from the expression for the voltage at the second interconnect. The interconnect coupling noise reaches a peak at a time determined for one of or, each one at a time, for the plurality of input voltages.
Advantages of the invention will be set forth, in part, in the description that follows and, in part, will be understood by those skilled in the art from the description herein. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims and equivalents.